1. Field of the Invention
This invention relates to a MOS-type integrated circuit for use as an output circuit element of a high breakdown-voltage integrated circuit.
2. Description of the Related Art
In the conventional output circuit of a high breakdown-voltage integrated circuit, a p-channel MOSFET having high breakdown voltage and serving as a level shifter, and an n-channel D-MOSFET having high breakdown voltage, are in different island regions of a silicon semiconductor substrate, and are electrically isolated from each other.
The structure of this output circuit will be explained, with reference to FIG. 1 showing an essential part thereof. After an oxide (not shown) is deposited on a surface of a p-type silicon semiconductor substrate 50 having boron-concentration of about 5.times.10.sup.14 /cm.sup.3, openings are formed in the oxide film at predetermined locations by means of photo lithography. Through the openings, antimony (Sb) is doped in the substrate 50. Then, a layer 51, having a phosphorus concentration of 1.times.15.sup.15 /cm.sup.3, is epitaxially formed on the substrate, thus forming buried regions 52 having an antimony concentration of about 10.sup.18 /cm.sup.3. p-isolating regions 53, having a surface impurity-concentration of about 1.times.10.sup.19 /cm.sup.3, are formed in the n--epitaxial layer 51, defining island regions. Further, deep n-regions 54, having a surface impurity-concentration of about 1.times.10.sup.19 /cm.sup.3, are formed at the both sides of the buried regions 52. In the upper end portion of the deep n-region 54 of one of the buried regions 52, n-region 55, having a surface arsenic(As)-concentration of about 1.times.10.sup.20 /cm.sup.3, is formed such that it is in ohmic contact with an electrode to be formed later.
A p--region 56, having a surface boron-concentration of about 1.times.10.sup.17 /cm.sup.3, is formed in one of the island regions of the n--epitaxial layer 51. In the p-region 56, n+-regions 57, having a surface As-concentration of about 1.times.10.sup.20 /cm.sup.3, are formed. A p+-region 58 is formed between the regions 57. The region 58 has a surface boron-concentration of about 1.times.10.sup.20 /cm.sup.3. On the other hand, in the other island region, an n--region 59, having a phosphorus concentration of about 1.times.10.sup.17 /cm.sup.3, is formed such that it contacts one of the deep n-regions 54. In the region 59, a p+-region 60 and an n+-region 61 are formed such that they contact each other. The region 60 has a surface boron-concentration of about 1.times.10.sup.20 /cm.sup.3, and the region 61 has a surface arsenic-concentration of about 1.times.10.sup.20 /cm.sup.3. Moreover a p-region 62 is formed such that it contacts the region 59. The region 62 is formed by doping boron about 5.times.10.sup.16 /cm.sup.3 , and has a large Xj. In the region 62, a p-region 63 is formed which has a surface boron-concentration of about 1.times.10.sup.20 /cm.sup.3.
The pn junctions formed of the above-described various impurity regions are exposed in the surface of the layer 51, and are protected by an insulating layer 64. While the layer 64 is shown as one layer in FIG. 1, it is formed of a CVD oxide layer and a thermally oxidized film. Polycrystal silicon layers 65 are buried in the insulating layer 64. A gate electrode 66, a source electrode 67 and a drain electrode 68 made of Al or Al alloy are provided at related openings. Each opening is formed by removing part of the insulating layer 64 above the polycrystal silicon layer 65. A resistor 69 made of polycrystal silicon is formed on the insulating layer 64, and connected to the source and drain electrodes 67 and 68.
As is described above, the p-channel MOSFET and n-channel MOSFET are in different island regions of the conventional MOS-type integrated circuit. This structure makes the circuit have a large total parasitic capacitance as much as that of two MOSFETs, since parasitic capacitance is proportional to the area of an element. This being so, an extra amount of current is charged or discharged for the parasitic capacitance during the operation of the circuit, inevitably increasing the power consumption, and also increasing the time required for the charge/discharge and hence decreasing the operation speed.